MITSUBISHI HA-ME43B Market price | HA-ME43B Introduction

Input and output points: 2048 points.
Input / output data points: 2048 points.
Program capacity: 30K.
Basic command processing speed (LD command) s:1.0.
Each scanning process. Focus on the input signal sampling. Focus on the output signal to refresh.
Input refresh process. When the input port is closed,
Program in the implementation phase, the input end of a new state, the new state can not be read HA-ME43B
Only when the program is scanned, the new state is read.
A scan cycle is divided into the input sample, the program execution, the output refresh.
The contents of the component image register are changed with the change of the execution of the program.
The length of the scan cycle is determined by the three.
CPU the speed of executing instructions.
Time of instruction.
Instruction count.
Due to the adoption of centralized sampling.
Centralized output mode.
There exist input / output hysteresis phenomena, i.e., the input / output response delay.
User program storage capacity: it is a measure of how much the user application can store the number of indicators.
Usually in words or K words as units. 16 bit binary number is a word,
Every 1024 words are 1K words. PLC to store instructions and data in words.
General logical operation instructions each account for 1 words. Timer / counter,
Shift instruction accounted for 2 words. Data operation instructions for 2~4. Input and output (DC/ differential).
Input points: 12 points (DC5V/DC24V/ differential universal).
Pulse input speed: the highest pulse/s 8M (2MHz).
Output points: 8 points (DC5V ~ DC24V) 6 points (differential).
Pulse output speed: the highest pulse/s 8M (2MHz).
High speed and stable input / output response
The high speed response can be achieved without the CPU module''s operation and bus performance,
Stable input and output response through hardware processing.
LD40PD01 is equipped with an external input and output interface and FPGA,
Therefore, high speed control can be realized without the influence of the scanning time of the CPU module and the bus performance (the input and output response time of the s instruction is realized).
Can achieve stable input and output response (processing time of the deviation of the ns level).
Through the intuitive tools for FPGA settings.
In the FPGA design process can be omitted in the past must be designed to deal with (HDL description, logic synthesis and time verification),
Reduce working hours. After receiving the product can be used immediately to verify the use of special tools, can significantly shorten the design time.
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